It is often desirable to generate signals at lower frequencies or speeds than an input signal. Divider circuitry is often used to receive an input signal and to provide a divided version of this input signal. The divided version of the input signal is at a lower frequency or rate than the input signal. For example, it may be desirable to generate one or more slower clock signals from a faster input clock signal. For example, if a 500 MHz clock signal were desired from a 3.0 GHz clock input signal, divider circuitry that divides this input clock signal by six (divide-by-6) could be used to achieve the desired output clock signal.
Further, it is often desirable to have the divider circuitry be programmable to allow different divided output signals to be generated. For example, with respect to many radio frequency (RF) receivers, there is a need to tune to different broadcast channels. This tuning is often accomplished using mixer circuitry to down-convert desired channels within the incoming RF signals to a lower intermediate frequency (IF) prior to further processing. This conversion of a desired channel with a particular center frequency (fC) can be achieved by mixing the incoming RF signal spectrum with a mixing signal that is offset in frequency from the center frequency (fC) by the desired IF. This mixing signal is typically based upon an oscillation signal generated by local oscillator (LO) circuitry. If the oscillation output signal begins at a higher frequency, programmable divider circuitry can be used to reduce the frequency of the oscillation signal to the desired frequency for the mixing signal.
FIG. 1A (Prior Art) is a block diagram for prior programmable divider circuitry 100. This divider circuitry utilizes a plurality of N cascaded divider cells (DIV 2/3) 102A, 102B . . . 102C, 102D. Each of these divider cells 102A, 102B . . . 102C, 102D provide either a divide-by-2 mode or a divide-by-3 mode of operation based upon a programmable input signal 114A, 114B . . . 114C, 114D received at the programming port (pi) for each cell and based upon a modulus input signal (modIN) received from the adjacent divider cell. Each of these divider cells 102A, 102B . . . 102C, 102D is configured to receive an input signal (FIN), to receive a modulus input signal (modIN), to generate an output signal (FOUT), and to generate a modulus output signal (modOUT). And these cascaded divider cells 102A, 102B . . . 102C, 102D are connected together.
More particularly, for the embodiment depicted, divider cell 102A (#1) receives the overall input signal (IN) 104 as its input signal (FIN), receives a programming signal (p0) 114A as its programming signal (pi), receives a modulus signal (mod1) 110A from divider cell 102B as its modulus input signal (modIN), and outputs a divided frequency signal (FO1) 106A as its output signal (FOUT). Divider cell 102B (#2) receives the divided frequency signal (FO1) 106A as its input signal (FIN), receives a programming signal (p1) 114B as its programming signal (pi), receives a modulus signal (mod2) 110B from the next divider cell (not shown) as its modulus input signal (modIN), outputs a divided frequency signal (FO2) 106B as its output signal (FOUT), and outputs a modulus output signal (mod1) 110A as its modulus output signal (modOUT). Divider cell 102C (#3) receives a divided frequency signal from the previous divider cell (not shown) as its input signal (FIN), receives a programming signal (pN−2) 114C as its programming signal (pi), receives a modulus signal (modN−1) 110C from divider cell 102D as its modulus input signal (modIN), outputs a divided frequency signal (FON−1) 106C as its output signal (FOUT), and outputs a modulus output signal as its modulus output signal (modOUT). Divider cell 102D (#4) receives a divided frequency signal (FON−1) 106C from divider cell 102C as its input signal (FIN), receives a programming signal (pN−1) 114D as its programming signal (pi), receives a fixed signal 110D (e.g., logic high level “1”) as its modulus input signal (modIN), outputs a divided frequency signal (FoN) 106D as its output signal (FOUT), and outputs a modulus output signal (modN−1) 110C as its modulus output signal (modOUT). It is noted that the modulus output signal for the first divider cell 102A is not used in the embodiment depicted.
The divider output signal (OUT) 112 for the divider circuitry 100 is taken from the modulus output signal (modi) 110A generated by divider cell 102B. The operation of this divider circuitry 100 produces a signal that is delayed in time (i.e., divided in frequency) according to the following equation:TOUT=[2N+(2N−1)pN−1+(2N−2)pN−2+ . . . +(2)p1+p0]TIN,where TIN represents the clock period for the input signal (IN) 104, TOUT represents the clock period for the output signal (OUT) 112, N is the number of cascaded divider cells, and p0, p1 . . . , pN−2, pN−1 represent the programming signals for the cascaded divider cells. Thus, as is seen by this equation for TOUT, the available division ratios are determined by the number of cells (N), with the minimum division ratio being 2N and the maximum division ratio being 2N+1−1. For example, where N=2, the equation for the output clock cycle time (TOUT) to the input clock cycle time (TIN) is represented by TOUT=[4+2p1+p0]TIN, and the available division ratios are 4, 5, 6 and 7. With respect to the programming signal (p1p0), a divide-by-4 is selected with p1p0=00; a divide-by-5 is selected with p1p0=01; a divide-by-6 is selected with p1p0=10; and a divide-by-7 is selected with p1p0=11.
In operation, if the programming input signal for a divider cell is a logic low or “0,” then that divider cell will always operate in a divide-by-2 mode. If the programming signal for a divider cell is a logic high or “1,” then that divider cell will operate in a divide-by-2 mode when its modulus input signal is a logic low or “0,” or it will operate in a divide-by-3 mode when its modulus input signal is a logic high or “1.” Because the final divider cell 102D has its modulus input (modIN) tied to a fixed logic high signal (“1”) 110D, the final divider cell 102D will always operate in a divide-by-3 mode when its programming input signal (pi) is a logic high or “1.”
Where N=2, for example, a divide-by-4 or a divide-by-5 will be provided when p1=0, and a divide-by-6 or a divide-by-7 will be provided when p1=1. For divide-by-4 and divide-by-5 modes of operation, the second divider cell 206B will divide by two in both modes. And in the divide-by-5 mode, the first divider cell 206A will swallow one extra input cycle for each output period of the second divider cell 206B (i.e., the output will be longer by one extra input cycle). For divide-by-6 and divide-by-7 modes of operation, the second divider cell 206B will divide by three in both modes. And in the divide-by-7 mode, the first divider cell 206A will swallow one extra input cycle for each output period of the second divider cell 206B (i.e., the output will be longer by one extra input cycle).
FIG. 1B (Prior Art) is a circuit diagram of an embodiment for programmable divider cell circuitry (DIV 2/3) 150 that can be used for divider cells 102A, 102B . . . 102C, 102D in FIG. 1A. Divider cell circuitry 150 receives an input signal 162 having an input frequency (FIN). Divider cell circuitry 150 also generates an output signal 164 having an output frequency (FO). The divider cell circuitry 150 also receives an input modulus signal (modIN) 184 and generates an output modulus signal (modOUT) 182. The circuitry with the divider cell circuitry 150 is organized as prescaler logic 160 and end-of-cycle logic 180. The prescaler logic 160 includes an AND gate 166, a D flip-flop latch (Dlatch 1) 168 and a D flip-flop latch (Dlatch 2) 170. The end-of-cycle logic 180 includes an AND gate 192, an AND gate 188, a D flip-flop latch (Dlatch 3) 186 and a D flip-flop latch (Dlatch 4) 170.
Looking in more detail to the prescaler logic 160, the AND gate 166 receives the output signal 164 and divider selection signal (2/3) 165 from the end-of-cycle logic 180 that determines whether the divider circuitry 2/3 is dividing by two or by three. The D flip-flop latch 168 receives the output of AND gate 166 as its data (D) input and receives the input signal 165 as its clock (CLK) input. The output (Q) of the D flip-flop latch 168 is received as the data (D) input for the D flip-flop latch 170. The D flip-flop latch 170 also receives an inverted version of the input signal 162 as its clock (CLK) input. The inverted output (Q_bar) of D flip-flop latch 170 is provided as the output signal 164, and the non-inverted output (Q) is provided to AND gate 192 within the end-of-cycle logic 180. It is noted that “Q_bar” as used herein represents the Q-overscore symbol within the drawings, which is the inverted version of the Q output signal. It is also noted that the open circle in front of inputs within the drawings, such as the clock (CLK) input for D flip-flop latch 170, indicates that an inverted version of the connected signal is being received.
Looking in more detail to the end-of-cycle logic 180, the AND gate 192 receives the non-inverted output (Q) from D flip-flop latch 170 and also receives the modulus input (modIN) 184. The output of AND gate 192 is received as the data (D) input for D flip-flop latch 190. The D flip-flop latch 190 also receives the input signal 162 as its clock (CLK) input and provides the modulus output signal (modOUT) 182 as its non-inverted output signal (Q). This non-inverted output signal (Q) from D flip-flop latch 190 is received as an input to AND gate 188 along with the programming input signal (pi) 152. The output of AND gate 188 is provided as the data (D) input for D flip-flop latch 186. D flip-flop latch 186 also receives an inverted version of the input signal 162 as its clock (CLK) input. The inverted output signal (Q_bar) from D flip-flop latch 186 provides the divider selection signal (2/3) 165.
It is noted that the D flip-flop latches operate such that the signal logic level presented at the data input (D) at each rising clock edge on the clock input (CLK) is provided as the output (Q) for the D flip-flop latch. In other words, the D flip-flop latches operate such that the signal logic level presented at the data input (D) is transparent to the output (Q) when the clock input (CLK) level is high. When the clock input (CLK) level is low, the output value (Q) is held, and it is insensitive to the input (D). Further, the operation of the divider circuitry shown in FIGS. 1A and 1B is further described in the following article: Vaucher, A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology, IEEE JSSC, Vol. 35, No. 7, pages 1039-1045 (July 2000), which is hereby incorporated by reference in its entirety.
Although the cascaded divide-by-2/3 (DIV 2/3) cells described in FIGS. 1A-1B provide a useful solution for programmable divider circuitry that provides integer division ratios from 2N to 2N+1−1, problems can arise due to the duty cycles generated by this divider circuitry. For example, where N=2 and division ratios 4, 5, 6 and 7 are selectable, the clock cycles for divide-by-4 are 2TIN high and 2TIN low or about 50% duty cycle. The clock cycles for divide-by-5 are 2TIN high and 3TIN low or about 40% duty cycle. The clock cycles for divide-by-6 are 2TIN high and 4TIN low or about 33% duty cycle. And the clock cycles for divide-by-7 are 2TIN high and 5TIN low or about 29% duty cycle. These differences in duty cycles, for example, can introduce undesirable errors for particular solutions that use this divider circuitry.